1. Field of the Invention
The present invention relates to a semiconductor apparatus such as a large scale integrated circuit (referred to as an LSI hereinafter), and more particularly, to a semiconductor apparatus including semiconductor devices fabricated on a wafer in a high density and in a large scale integration.
2. Description of Related Art
Recently, there have been great demands for miniaturizing electronic apparatuses such as office automation equipment, audio and/or visual equipment, for various kinds of functions thereof, and for reducing the cost thereof. Accompanying with this, it has been necessary to fabricate semiconductor apparatuses in a high density and in a large scale integration, which are used in these electronic apparatuses.
In order to satisfy these demands, the Wafer Scale Integration method (referred to as a WSI method hereinafter) has been studied, to which the concept of the conventional LSI was extended. In a semiconductor apparatus fabricated by the WSI method, multiple chips are fabricated on one wafer in a large scale integration, wherein the multiple chips having various kinds of functions are electrically connected to each other through interconnection films.
Since the interconnection films thereof are formed on the wafer in a similar manner to fabricating conventional LSIs such as the wafer process technique, the semiconductor apparatuses fabricated by the WSI method have the following advantages, as compared with a conventional semiconductor apparatus wherein a plurality of electronic circuit components such as conventional LSI packages are formed on a printed circuit substrate.
(a) Devices and interconnection films for connecting the devices can be arranged in a high density. PA1 (b) Signals having higher frequencies can be handled therein, a high signal to noise ratio can be obtained, and power consumption can be lowered, because the length of each interconnection film can be shortened. PA1 (c) There is a possibility of lowering the cost of the semiconductor apparatus since the multiple chips having various kinds of functions can be fabricated on one wafer utilizing the wafer process technique. PA1 an electrically insulating circuit substrate on which electrically conductive interconnection films are separately formed; PA1 at least one semiconductor chip having electrodes, the semiconductor chip being bonded on the circuit substrate; PA1 at least two through holes being formed in the semiconductor chip so as to pierce the semiconductor chip in the direction of the thickness thereof; and PA1 electrically conductive bodies being formed in the through holes, respectively, each of the conductive bodies electrically connecting a predetermined electrode of the semiconductor chip to a predetermined interconnection film formed on the circuit substrate. PA1 an electrically insulating circuit substrate on which electrically conductive interconnection films are separately formed; PA1 at least one semiconductor chip having electrodes, the semiconductor chip being bonded on the circuit substrate; and PA1 at least two electrically conductive films being separately formed on a side surface of the semiconductor chip, each of the conductive films electrically connecting a predetermined electrode of the semiconductor chip to a predetermined interconnection film formed on the circuit substrate. PA1 an electrically insulating circuit substrate on which electrically conductive interconnection films are separately formed; PA1 a plurality of semiconductor chips being bonded so as to be stacked on the circuit substrate, each of the plurality of semiconductor chips having electrodes; and PA1 electrical connection means, each of the connection means electrically connecting a predetermined electrode of each of the semiconductor chips to a predetermined interconnection film formed on the circuit substrate. PA1 a plurality of semiconductor chips including circuit components having electrodes, the semiconductor chips being bonded onto each other so as to form an assembled chip; and PA1 electrically conductive interconnection films being separately formed on the plurality of semiconductor chips, each of the interconnection films electrically connecting respective predetermined electrodes of the plurality of semiconductor chips of the assembled chip to each other.
However, because the semiconductor apparatus fabricated by the WSI method has a much larger area than that of the conventional LSI of one chip, the whole wafer is dealt as defective in the case that there is at least one defective on the wafer. Therefore, there is such a problem that the yield thereof becomes very low. Furthermore, in the semiconductor apparatus fabricated by the WSI method, since the devices and the interconnection films for connecting the devices are monolithically formed on the wafer utilizing a fabrication process performed for every wafer, there are such disadvantages that it is difficult to mixedly form various kinds of devices on one wafer, and also the number of the fabrication processes increases. Due to this, the devices to be formed on the same wafer are limited to particular devices, and also the range of the applications of the WSI method becomes very narrow.
In order to solve the aforementioned problems, a fabrication method for a multichip substrate system has been proposed. A multichip substrate system is fabricated as follows.
First of all, various kinds of wafers on which devices such as LSIs are formed are diced so as to be divided into a plurality of chips, and nondefective chips are picked up among the plurality of diced chips. Thereafter, only the nondefective chips are fabricated as components on an electrically insulating substrate. Then, there can be obtained a multichip substrate system having a scale larger than that of the system formed on each chip.
FIG. 1 is a cross-sectional view showing a conventional semiconductor apparatus fabricated by the aforementioned fabrication method for the multichip substrate system.
Both semiconductor chips 200i and 200k with integrated circuit components formed on the top surface thereof are coated with an electrically insulating film 271, and the semiconductor chips 200i and 200k are bonded on predetermined positions of an electrically insulating substrate 273 through an adhesive layer 274 so as to be apart from each other by a predetermined distance. A mediation chip 200j without any circuit components is bonded at a position between the semiconductor chips 200i and 200k on the insulating substrate 273 through the adhesive layer 274, in order to keep the top surface thereof flat, wherein the mediation chip 200j is coated with the insulating film 271. Similarly, various kinds of chips are bonded on the insulating substrate 273 through the adhesive layer 274.
Respective interconnection films 280 formed on the semiconductor chips 200i and 200k are electrically connected to each other through an interconnection film 275, which is coated with an electrically insulating film 276. The interconnection film 275 is electrically connected to an interconnection film 277a and a connection pad 277b, which are formed on the insulating film 276, through a hole 276a formed at a predetermined position of the insulating film 276. The connection pad 277b is electrically connected to an interconnection film 278 formed on the insulating substrate 273 through a lead wire 279.
However, there are the following problems in the semiconductor apparatuses fabricated by the aforementioned conventional fabrication methods.
In the multichip substrate system, because it is necessary to electrically connect multiple interconnection films formed on the substrate to external terminals formed on another substrate or the main body of the semiconductor apparatus through the connection pads formed on the outer edge portions of the substrate, there is such a problem that the number of the connection pads increases steeply. Furthermore, in the multichip substrate system, the area of the substrate on which the devices and the interconnection films are formed becomes remarkably larger than that of the conventional LSI chip. On the other hand, the area of the outer edge portions where the connection pads are to be formed is relatively small. Therefore, the problem of the increase of the connection pads which accompanies the aforementioned large scale integration becomes extremely serious.
Further, in conventional connection methods such as the wire bonding method and the tape carrier method, which have been widely used as a method of connecting the external terminals and the connection pads formed on the substrate, it is necessary to form each pad having a relatively large area in the range from about 80 .mu.m square to about 100 .mu.m square in order to keep a predetermined connection strength between each pad and connector such as a lead wire. Furthermore, taking into consideration a shift of the connection point of each lead wire from a predetermined connection point on each connection pad upon a connection process of bonding each lead wire, it is necessary to provide a gap between the adjacent pads larger than several tens of .mu.m. Due to this, there are such problems that the enhancement of the integration makes the ratio of the area where the pads are formed to that of the substrate extremely large, and also the manufacturing cost thereof remarkably increases.
Because the pads are formed on the outer edge portions of the substrate, the pattern of the interconnection films for electrically connecting interconnection terminals formed on each chip to respective pads becomes complicated. Therefore, it becomes difficult to design the semiconductor apparatus optimally, and respective costs of the design and the fabrication process remarkably increases. Because respective chips are arranged in a two-dimensional array on the substrate, this sets a limit to arrange respective chips in a higher density and to miniaturize them, and also leads to the increase in the length of each of the interconnection films for electrically connecting a chip to the pads and the interconnection film for electrically connecting respective chips. Therefore, the increase in the length thereof causes the following problems: the devices and the interconnection films cannot be arranged in a high density, a high signal to noise ratio cannot be obtained, and power consumption cannot be lowered.